1. Field of the Invention
This invention generally relates to a semiconductor package structure and method for fabricating the same, and more specifically, to a heat dissipation semiconductor package structure that provides semiconductor chip with efficient heat dissipation path and method for fabricating the same.
2. Description of Related Art
In order to protect semiconductor chips of conventional semiconductor packages from being contaminated by external water and dust, the semiconductor chips are encapsulated with an encapsulant for insulation purpose. However, as the encapsulant made of a package resin has poor heat conductivity, thermal conductivity coefficient of which is around 0.8 w/m° K, heat generated during operation of the semiconductor chips cannot be efficiently dissipated to the outside via the encapsulant, thereby causing heat accumulation and dramatically and adversely affecting performance and lifetime of the semiconductor chips. Therefore, the idea of adding a heat dissipation member in a semiconductor package is conceived so as to enhance heat dissipation efficiency of the semiconductor package.
However, if the heat dissipation member is also completely encapsulated by the encapsulant, heat generated by a semiconductor chip still must pass through the encapsulant before being dissipated to the outside. Accordingly, there is quite limited improvement in heat dissipation efficiency, and even worse, heat dissipation demand cannot be fulfilled. Therefore, one approach to efficiently dissipate heat generated by a semiconductor chip is to completely expose the heat dissipation member from the encapsulant, and another approach is to directly expose surface of a semiconductor chip from the encapsulant, thereby directly dissipating heat generated by the semiconductor chip via surface exposed to the air.
Please refer to FIG. 1A, which is a diagram of a semiconductor package disclosed by U.S. Pat. No. 5,450,283, wherein, surface of a semiconductor chip 11 of the semiconductor package 10 is directly exposed from an encapsulant 14 encapsulating the semiconductor chip 11. Since the top surface of the semiconductor chip 11 is exposed from the encapsulant 14 and directly contacts with the air, heat generated by the semiconductor chip 11 is capable of being dissipated directly to the air without the need of passing through the encapsulant 14, thus improving the heat dissipation efficiency.
However, referring to FIG. 1B, there are some disadvantages in fabricating the abovementioned semiconductor package 10. First, when the substrate 12 attached with the semiconductor chip 11 is disposed inside a mold cavity 15 of an encapsulation mold for a molding process to form the encapsulant 14, a tape 13 must be pre-adhered to the top wall of the mold cavity 15 such that the top surface of the semiconductor chip 11 can be abutted against the top wall of the mold cavity 15 through the tape 13 after the mold is closed, thereby avoiding flashing of the molding compound on the top surface of the semiconductor chip 11. However, if the overall height of the substrate 12 attached with the chip 11 is too low due to bad control of the attaching height of the semiconductor chip 11 on the substrate 12, the top surface of the semiconductor chip 11 cannot be efficiently abutted against the top wall of the mold cavity 15 through the tape 13 and therefore a gap is formed between the top surface of the semiconductor chip 11 and the top wall of the mold cavity 15. As a result, the molding compound for forming the encapsulant 14 will flash on the top surface of the semiconductor chip 11. As long as flash occurs on the top surface of the semiconductor chip 11, not only heat dissipation efficiency of the semiconductor chip 11 is decreased, but also appearance of finished product is adversely affected, Thus, a post process of deflashing is required to be performed, which however is time-consuming and increases the fabrication cost and can even lead to damage of finished product. On the other hand, if the overall height of the substrate 12 attached with the semiconductor chip 11 is too high, then pressing force of the semiconductor chip 11 abutting against the top wall of the mold cavity 15 through the tape 13 can be too strong, which can easily lead to crack of the semiconductor chip 11.
Meanwhile, closing force of the encapsulation mold is further transmitted to the semiconductor chip 13 through the tape 13, which also causes crack of the semiconductor chip 11. Therefore, yield of the finished products after encapsulation cannot be efficiently increased, and fabrication cost is difficult to be decreased.
In view of the abovementioned drawbacks of the prior art, U.S. Pat. No. 6,458,626, as shown in FIGS. 2A through 2C, U.S. Pat. No. 6,444,498, as shown in FIG. 3, and U.S. Pat. No. 6,699,731, as shown in FIG. 4, which are assigned to the same assignee as this application, disclose a semiconductor package with a heat dissipation member directly attached to a semiconductor chip without causing problem of flash or chip crack, or disclose a semiconductor package with surface of a semiconductor chip directly exposed to the air.
As shown in FIG. 2A, an interface layer 25 that has poor bonding with encapsulant is formed on surface of a heat dissipation member 21 to be exposed to the air. Then, the heat dissipation member 21 is attached on a semiconductor chip 20 on a substrate 23. Subsequently, a package molding process is performed so as to form an encapsulant 24 to completely encapsulate the heat dissipation member 21 and the semiconductor chip 20, and the encapsulant 24 also covers the interface layer 25 of the heat dissipation member 21. Therefore, mold cavity of the encapsulation mold used in the package molding process has a depth greater than the overall height of the semiconductor chip 20 and the heat dissipation member 21, consequently, the encapsulation mold will not contact the heat dissipation member 21 and accordingly crack of the semiconductor chip 20 caused by pressing force is avoided. Next, a cutting process is performed as shown in FIG. 2B, and also the encapsulant 24 on the heat dissipation member 21 is removed, wherein, if the bonding force between the interface layer 25, such as a gold plating layer, and the heat dissipation member 21 is greater than the bonding force between the interface layer 25 and the encapsulant 24, when the encapsulant 24 is removed, the interface layer 25 will be left on the heat dissipation member 21. Meanwhile, since the interface layer 25 has poor bonding with the encapsulant 24, no encapsulant residue is left on the interface layer 25, as shown in FIG. 2C, thereby avoiding the flash problem. On the other hand, if the bonding force between the interface layer 25, such as an adhesive tape made of a polyimide resin, and the heat dissipation member 21 is less than the bonding force between the interface layer 25 and the encapsulant 24, when the encapsulant 24 is removed, the interface layer 25 is removed together with the encapsulant 24, as shown in FIG. 3, which also avoids the flash problem.
Furthermore, as shown in FIG. 4, which is a cross-sectional diagram of one semiconductor package according to U.S. Pat. No. 6,699,731, wherein a metal cover sheet 33 with an interface layer 333 is formed on a semiconductor chip 31. The interface layer 333 has different coefficient of thermal expansion from molding compound for forming the encapsulant 34, as a result, the interface layer 333 of poor bonding nature will delaminate from the semiconductor chip 31 and the encapsulant 34 around the semiconductor chip 31. Therefore, the interface layer 333, the cover sheet 33, and the molding compound 340 on the cover sheet 33 can be easily peeled off from surfaces of the semiconductor chip 31 and encapsulant 34 around the semiconductor chip 31, thereby exposing surface of the semiconductor chip 31 from the encapsulant 34 and directly dissipating heat generated by the semiconductor chip 31 to the air through the exposed surface. In addition, in the package molding process, since surface of the semiconductor chip 31 is completely covered by the interface layer 333, no molding compound residual is left on the surface of the semiconductor chip 31, consequently there is no need to perform any post process for removing flash, thereby decreasing the package cost and ensuring a better appearance of finished product of the semiconductor package.
However, complicated process and high fabrication cost of the fabrication processes of semiconductor packages restrict their practical application in the semiconductor package industry.
Hence, it is a highly urgent issue in the industry for how to provide a heat dissipation package structure and method for fabricating the same that can prevent semiconductor chip from being damaged by press force during a package molding process and meanwhile has simple fabrication process and low cost.